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cy8c24533 psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-14643 rev. *d revised december 05, 2008 features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3.0 to 5.25v operating voltage ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? 4 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 8-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? 4 digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? crc and prs modules ? full-duplex uart ? multiple spi ? masters or slaves ? connectable to all gpio pins ? complex peripherals by combining blocks ? high-speed 8-bit sar adc op timized for motor control precision, programmable clocking ? internal 5% 24/48 mhz oscillator ? high accuracy 24 mhz with optional 32 khz crystal and pll ? optional external oscillator, up to 24 mhz ? internal oscillator for watchdog and sleep flexible on-chip memory ? 8k bytes flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash programmable pin configurations ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to ten analog inputs on gpio ? two 30 ma analog outputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory digital system sram 256 bytes interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 8k digital block array multiply accum. internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog ref analog input mu xi n g i 2 c po r t 2 po r t 1 po r t 0 analog dr iv er s system bus an alo g block array 1 row 4 blocks 2 columns 4 blocks sar8 adc po r t 3 logic block diagram [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 2 of 34 psoc functional overview the psoc family consists of many mixed-signal array with on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip prog rammable device. psoc devices include configur able blocks of analog a nd digital logic, and programmable interconnects. this architecture allows the user to create customized peripheral co nfigurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and config- urable io are included in a range of convenient pinouts and packages. the psoc architecture, as shown in the logic block diagram on page 1, is comprised of four main areas: psoc core, digital system, analog system, and syst em resources. configurable global busing allows all the device resources to be combined into a complete custom system. t he psoc cy8c24x33 family can have up to three io ports that connect to the global digital and analog interconnects, pr oviding access to four digital blocks and four analog blocks. psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, memory, clocks, and configurable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micropro- cessor. the cpu utilizes an interrupt controller with 11 vectors, to simplify programming of real time embedded events. program execution is timed and protect ed using the included sleep and watch dog timers (wdt). memory encompasses 8 kb of fl ash for program storage, 256 bytes of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash utilizes four protection levels on blocks of 64 bytes, allowing customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24 mhz imo (internal main oscillator) accurate to 5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system clock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external inter- facing. every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. digital system the digital system is composed of 4 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24 , and 32-bit peri pherals, which are called user module references. figure 1. digital system block diagram the digital peripheral configurations include: pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity (up to 1) spi master and slave (up to 1) i2c slave and master (one available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to one) pseudo random sequence generators (8 to 32 bit) the digital blocks can be con nected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, wher e the number of blocks varies by psoc device family. this allows you the optimum choice of system resources for your application. family resources are shown in the table titled psoc device character- istics on page 4. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect po r t 3 po r t 1 po r t 0 po r t 2 [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 3 of 34 analog system the analog system is composed of an 8-bit sar adc and four configurable blocks. the progr ammable 8-bit sar adc is an optimized adc that runs up to 300 ksps, with monotonic guarantee. it also has the feat ures to support a motor control application. each analog block is comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific appli- cation requirements. some of the more common psoc analog functions (most available as user modules) are: filters (2 and 4 pole band pass, low-pass, and notch) amplifiers (up to 2, with selectable gain to 48x) instrumentation amplifiers (1 with selectable gain to 93x) comparators (up to 2, with 16 selectable thresholds) dacs (up to 2, with 6- to 9-bit resolution) multiplying dacs (up to 2, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive as a core resource) 1.3v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. the analog column 0 contains the sar8 adc block rather than the standard sc blocks. figure 2. analog system block diagram acb00 acb01 block array array input configuration aci1[1:0] aci0[1:0] p0 [ 6 ] p0 [ 4 ] p0 [ 2 ] p0 [ 0 ] p2 [ 2 ] p2 [ 0 ] p2 [ 6 ] p2 [ 4 ] refin agndin p0 [ 7 ] p0 [ 5 ] p0 [ 3 ] p0 [ 1 ] p2 [ 3 ] p2 [ 1 ] re f e r e n ce ge ne r ator s agndin ref in bandgap ref hi ref lo agnd asd11 asc21 interface to dig ital sys t e m m8c interface (address bus, data bus, etc.) analog reference 8-bit sar adc aci2[3:0] p0[7:0] [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 4 of 34 additional system resources system resources, some of which have been previously listed, provide additional ca pability useful to complete systems. additional resources include a multiplier, decimator, low voltage detection, and power on reset. brief statements describing the merits of each system resource follow: digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using di gital psoc blocks as clock dividers. a multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, includ ing adcs and dacs. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. the following tabl e lists the resources available for specific psoc device groups. getting started the quickest path to understanding the psoc silicon is by reading this data sheet and us ing the psoc designer integrated development environment (ide). th is data sheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc cy8c24533 mixed-signal array technical reference manual . for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cyp ress.com/psoc . to determine which psoc device meets your requirements, navigate through the psoc decision tree in the application note an2209 at http://www.cypress.com and select application notes under the design resources. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress. com/onlinestore . technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog and capsense. go to http://www.cypress.com . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com , click on design support located at the top of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support . application notes a long list of application notes c an assist you in every aspect of your design effort. to view the psoc application notes, go to http://www.cypress. com/psocapnotes . table 1. psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sar8 adc cy8c29x66 up to 64 4 16 12 4 4 12 no cy8c27x43 up to 44 2 8 12 4 4 12 no cy8c24x94 56 1 4 48 2 2 6 no cy8c24533 up to 26 1 4 12 2 2 4 yes cy8c24x23a up to 24 1 412226no cy8c21x34 up to 28 142802 4 [1] no cy8c21x23 16 1 4 8 0 2 4 [1] no cy8c20x34 up to 28 0 0 28 0 0 3 [2] no notes 1. limited analog functionality . 2. two analog blocks and one capsense. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 5 of 34 development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devic es. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp (refer figure 3 ). psoc designer helps the customer to select an operating configuration for the psoc, writ e application code that uses the psoc, and debug the application. this system provides design database management by projec t, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high level c language compiler developed specifically for the devices in the family. figure 3. psoc designer subsystems psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reco nfiguration. dynamic configu- ration allows for changing configurations at run time. psoc designer sets up power on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected com ponents and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and r egenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controlle r, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the psoc family of devi ces. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc archit ecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. commands results psoc designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer inte rfa c e context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc designer [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 6 of 34 debugger the psoc designer debugger s ubsystem provides hardware in-circuit emulation, allowing t he designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu re gisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays online, context- sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, mu ltiplexers, buses and to the io pins. iterative development cycl es permit you to adapt the hardware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer integrated development environm ent (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library contains over 50 common peripherals such as adcs, dacs timers, counters, uarts, and other not-so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes t he basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pu lse width modulator user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high-level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal oper ation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you also configure the cloc k source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the high-level user module api functions. figure 4. user module/source code development flows debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 7 of 34 the next step is to write your main program, and any sub-routines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as necessary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 6 on page 13 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h? or ?b? are decimal. table 2. acronyms used acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eeprom electrically erasable pr ogrammable read-only memory fsr full scale range gpio general purpose io io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator ram random access memory rom read only memory sc switched capacitor table 2. acronyms used (continued) acronym description [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 8 of 34 pinouts the psoc cy8c24533 is available in a 28-pin ssop package. every port pin (labeled with a ?p?), except for vss and vdd in the following table and figure, is capable of digital io. 28-pin part pinout table 3. 28-pin part pinout (ssop) pin number cy8c24533 digital analog pin name description figure 5. cy8c24533 psoc device 1 io i p0[7] analog col mux ip and adc ip 2 io io p0[5] analog col mux ip and column o/p and adc ip 3 io io p0[3] analog col mux ip and column o/p and adc ip 4 io i p0[1] analog col mux ip and adc ip 5 io p2[7] gpio 6 io p2[5] gpio 7 io i p2[3] direct switched capacitor input 8 io i p2[1] direct switched capacitor input 9ioavref p3[0] [3] gpio/adc vref (optional) 10 io p1[7] i2c scl 11 io p1[5] i2c sda 12 io p1[3] gpio 13 io p1[1] [4] gpio, xtal input, i2c scl, issp scl 14 power vss ground pin 15 io p1[0] [4] gpio, xtal output, i2c sda, issp sda 16 io p1[2] gpio 17 io p1[4] gpio, external clock ip 18 io p1[6] gpio 19 io p3[1] [5] gpio 20 io i p2[0] direct switched capacitor input 21 io i p2[2] direct switched capacitor input 22 io p2[4] gpio 23 io p2[6] gpio 24 io i p0[0] analog col mux ip and adc ip 25 io i p0[2] analog col mux ip and adc ip 26 io i p0[4] analog col mux ip and adc ip 27 io i p0[6] analog col mux ip and adc ip 28 power vdd supply voltage legend : a = analog, i = input, and o = output. aio, p0[7] io, p0[5] io, p0[3] aio, p0[1] io, p2[7] io, p2[5] aio, p2[3] aio, p2[1] avref, io, p3[0] i2c scl, io, p1[7] i2c sda, io, p1[5] io, p1[3] i2c scl, issp scl, xtalin, io, p1[1] vss vdd p0[6], aio, ancolmux and adc ip p0[4], aio, ancolmux and adc ip p0[2], aio, ancolmux and adc ip p0[0], aio, ancolmux and adc ip p2[6], io p2[4], io p2[2], aio p2[0], aio p3[1], io p1[6], io p1[4], io, extclk p1[2], io p1[0], io, xtalout, issp sda, i2c sda ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 notes 3. even though p3[0] is an odd port, it resides on the left side of the pinout. 4. issp pin, which is not high z at por. 5. even though p3[1] is an even port, it resides on the right side of the pinout. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 9 of 34 register reference this chapter lists the registers of the cy8c24533 psoc device by using mapping tables, in offset order. for detailed register i nfor- mation, refer the psoc cy8c24533 mixed-signal array technical reference manual. register conventions abbreviations used the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 10 of 34 table 4. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 80 c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 asd11cr0 84 rw c4 prt1ie 05 rw 45 asd11cr1 85 rw c5 prt1gs 06 rw 46 asd11cr2 86 rw c6 prt1dm2 07 rw 47 asd11cr3 87 rw c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 d0 11 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw i2c_cfg d6 rw 17 57 asc21cr3 97 rw i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # saradc_dl 67 rw a7 dec_cr1 e7 rw dcb02dr0 28 # 68 a8 mul0_x e8 w dcb02dr1 29 w saradc_cr0 69 # a9 mul0_y e9 w dcb02dr2 2a rw saradc_cr1 6a rw aa mul0_dh ea r dcb02cr0 2b # 6b ab mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw ac acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw ad acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw ae acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw af acc0_dr2 ef rw 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 * 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 * 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd gray fields are reserved. # access is bit specific. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 11 of 34 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 4. register map bank 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access gray fields are reserved. # access is bit specific. table 5. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 asd11cr0 84 rw c4 prt1dm1 05 rw 45 asd11cr1 85 rw c5 prt1ic0 06 rw 46 asd11cr2 86 rw c6 prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 asc21cr0 94 rw d4 15 55 asc21cr1 95 rw d5 16 56 asc21cr2 96 rw d6 17 57 asc21cr3 97 rw d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 saradc_trs a8 rw imo_tr e8 w dcb02in 29 rw 69 saradc_trcl a9 rw ilo_tr e9 w dcb02ou 2a rw 6a saradc_trch aa rw bdg_tr ea rw 2b 6b saradc_cr2 ab # eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw saradc_lcr ac rw ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 acb00cr3 70 rw rdi0ri b0 rw f0 31 acb00cr0 71 rw rdi0syn b1 rw f1 32 acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 34 acb01cr3 74 rw rdi0lt1 b4 rw f4 35 acb01cr0 75 rw rdi0ro0 b5 rw f5 36 acb01cr1 76 rw rdi0ro1 b6 rw f6 gray fields are reserved. # access is bit specific. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 12 of 34 37 acb01cr2 * 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 5. register map bank 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access gray fields are reserved. # access is bit specific. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 13 of 34 electrical specifications this section presents the dc and ac electrical specifications of the cy8c24533 psoc device. for the latest electrical specifica tions, visit http://www.cypress.com/psoc . specifications are valid for -40 o c t a 85c and t j 100c, except where noted. refer to table 21 on page 22 for the electrical specificat ions on the internal main o scillator (imo) using slimo mode. the following table lists the units of me asure that are used in this section. table 6. units of measure symbol unit of measure symbol unit of measure c degree celsius w micro watts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nano ampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm w ohm mhz megahertz pa pico ampere m megaohm pf pico farad a micro ampere pp peak-to-peak f micro farad ppm parts per million h micro henry ps picosecond s microsecond sps samples per second v micro volts s sigma: one standard deviation vrms micro volts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 slimo mode=1 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 figure 6. voltage versus cpu frequency figure 7. imo frequency trim options [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 14 of 34 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. operating temperature table 7. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduces data retention time. recommended storage temperature is +25c 25c. extended duration storage tempera- tures above 65c degrades reliability. t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current in to any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma table 8. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedances by package on page 32. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 15 of 34 dc electrical characteristics dc chip-level specifications the following table lists the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 9. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.0 ? 5.25 v see table 19 on page 21 . i dd supply current ? 5 8 ma conditions are vdd = 5.0v, t a = 25 c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. i dd3 supply current ? 3.3 6.0 ma conditions are vdd = 3.3v, t a = 25c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [6] ? 3 6.5 a conditions are with internal slow speed oscillator, vdd = 3.3v, -40c t a 55c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [6] ? 4 25 a conditions are with internal slow speed oscillator, vdd = 3.3v, 55c < t a 85c, analog power = off. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal. [6] ? 4 7.5 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40c t a 55c, analog power = off. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and external crystal at high temperature. [6] ? 5 26 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3 v, 55c < t a 85c, analog power = off. v ref reference voltage (bandgap) 1.28 1.30 1.33 v trimmed for appropriate vdd. vdd > 3.0v note 6. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this must be compare d with devices that have similar functions enabled. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 16 of 34 dc general purpose io specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 10. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (maximum 40 ma on even port pins (for example, p0[2], p1[4]), maximum 40 ma on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (maximum 100 ma on even port pins (for example, p0[2], p1[4]), maximum 100 ma on odd port pins (for example, p0[3], p1[5])). 100 ma maximum combined ioh budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 17 of 34 dc operational amplifier specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched cap psoc blocks. the guaranteed specifications are meas ured in the analog continuous time psoc bl ock. typical parameters apply to 5v at 25 c and are for design guidance only. table 11. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? vdd vdd - 0.5 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the character- istics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high vdd - 0.2 vdd - 0.2 vdd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? 300 600 1200 2400 4600 400 800 1600 3200 6400 a a a a a psrr oa supply voltage rejection ratio 52 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 18 of 34 dc low power compar ator spec ifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 12. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.2 ? vdd - 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the character- istics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ? ? db specification is applicable at high power. for all other bias modes (except high power, high opamp bias), minimum is 60 db. v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high is 5v only vdd - 0.2 vdd - 0.2 vdd - 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? 300 600 1200 2400 4600 400 800 1600 3200 6400 a a a a a psrr oa supply voltage rejection ratio 52 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd table 13. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 19 of 34 dc analog output buffer specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 14. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.1 0.5 x vdd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (vdd - 1.25) table 15. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 52 64 ? db v out > (vdd - 1.25) [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 20 of 34 dc analog reference specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the guaranteed specificat ions are measured through the anal og continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power levels for refhi and reflo refer to the a nalog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 16. 5v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.33 v ? agnd = vdd/2 vdd/2 - 0.04 vdd/2 - 0.01 vdd/2 + 0.007 v ? agnd = 2 x bandgap 2 x bg - 0.048 2 x bg - 0.030 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap bg - 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap 1.6 x bg - 0.022 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd/2 + bg - 0.10 vdd/2 + bg vdd/2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg - 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2 [6] (p2[6] = 1.3v) 2 x bg + p2[6] - 0.113 2 x bg + p2[6] - 0.018 2 x bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg - 0.130 p2[4] + bg - 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.133 p2[4] + p2[6] - 0.016 p2[4] + p2[6]+ 0.100 v ? refhi = 3.2 x bandgap 3.2 x bg - 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = vdd/2 ? bandgap vdd/2 - bg - 0.04 vdd/2 - bg + 0.024 vdd/2 - bg + 0.04 v ? reflo = bandgap bg - 0.06 bg bg + 0.06 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2 x bg - p2[6] - 0.084 2 x bg - p2[6] + 0.025 2 x bg - p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - bg - 0.056 p2[4] - bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.057 p2[4] - p2[6] + 0.026 p2[4] - p2[6] + 0.110 v table 17. 3.3v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.33 v ? agnd = vdd/2 vdd/2 - 0.03 vdd/2 - 0.01 vdd/2 + 0.005 v ? agnd = 2 x bandgap not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap bg - 0.009 bg + 0.005 bg + 0.015 v ? agnd = 1.6 x bandgap 1.6 x bg - 0.027 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd column to column variation (agnd = vdd/2) -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2 [6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.075 p2[4] + p2[6] - 0.009 p2[4] + p2[6] + 0.057 v [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 21 of 34 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. dc por and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. refer the psoc cy8c24533 mixed-signal array technical reference manual for more information on the vlt_cr register. ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.048 p2[4]- p2[6] + 0.022 p2[4] - p2[6] + 0.092 v table 18. dc analog psoc block specifications symbol description min typ max units r ct resistor unit value (continuous time) ? 12.2 ? k table 19. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 0 2.85 0 2.95 3.06 4.37 4.50 4.62 4.71 2.45 0 2.92 0 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [7] 2.99 [8] 3.09 3.20 4.55 4.75 4.83 4.95 v 0 v 0 v 0 v 0 v 0 v v v table 17. 3.3v dc analog reference specifications (continued) symbol description min typ max units notes 7. always greater than 50 mv above v ppor (porlev=00) for falling supply. 8. always greater than 50 mv above v ppor (porlev=01) for falling supply. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 22 of 34 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. sar8 adc dc specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 20. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 3.3 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [9] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years table 21. sar8 adc dc specifications symbol description min typ max units notes v adcvref reference voltage at pin p3[0] when configured as adc reference voltage 3.0 ? 5.25 v the voltage level at p3[0] (when configured as adc reference voltage) must always be maintained to be less than chip supply voltage level on vdd pin. v adcvref < vdd. i adcvref current when p3[0] is configured as adc v ref 3 ??ma inl r-2r integral non-linearity [10] -1.2 ? +1.2 lsb the maximum lsb is over a sub-range not exceeding 1/16 of the full scale range. dnl r-2r differential non-linearity [11] -1 ? +1 lsb output is monatonic. note 9. a maximum of 36 x 50,000 bloc k endurance cycles is allo wed. this may be balanc ed between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycl es each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperatur e sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 10. at the 7f and 80 points, the maximum inl is 1.5 lsb. 11. for the 7f to 80 transition, the dnl specification is waived. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 23 of 34 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 22. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 22.8 24 25.2 [12],[13],[14] mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 7 on page 13 . slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 [12],[13],[14] mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 7 on page 13 . slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.093 24 24.6 [12],[13] mhz f cpu2 cpu frequency (3.3v nominal) 0.093 12 12.3 [13],[14] mhz f 48m digital psoc block frequency 0 48 49.2 [12],[13],[15] mhz refer to the ac digital block specifica- tions. f 24m digital psoc block frequency 0 24 24.6 [13],[15] mhz f 32k1 internal low speed oscillator frequency 15 32 75 khz f 32k2 external crystal oscillator ? 32.76 8 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.98 6 ? mhz is a multiple (x732) of crystal frequency. jitter24m2 24 mhz period jitter (pll) ? ? 600 ps t pllslew pll lock time 0.5 ? 10 ms t pllslewslow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 1700 2620 ms t osacc external crystal oscillator startup to 100 ppm ? 2800 3800 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 uw maximum drive level 32.768 khz crystal. 3.0v vdd 5.5v, -40c t a 85c jitter32k 32 khz period jitter ? 100 ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [12],[14] mhz trimmed. using factory trim values. jitter24m1r 24 mhz period jitter (imo) root mean squared ? ? 600 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s notes 12. 4.75v < vdd < 5.25v. 13. accuracy derived from internal main oscillator with appropriate trim for vdd range. 14. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimming for operation at 3.3v. 15. see the individual user module data sheets for information on maximum frequencies for user modules. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 24 of 34 figure 8. pll lock timing diagram figure 9. pll lock for low gain setting timing diagram figure 10. external crystal oscillator startup timing diagram figure 11. 24 mhz period jitter (imo) timing diagram figure 12. 32 khz period jitter (eco) timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os jitter24m1 f 24m jitter32k f 32k2 [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 25 of 34 ac general purpose io specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 13. gpio timing diagram table 23. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 26 of 34 ac operational amplifier specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v. table 24. 5v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz table 25. 3.3v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%) (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 27 of 34 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 14. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 15. typical opamp noise 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz ) dbv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 28 of 34 ac low power compar ator spec ifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. ac digital block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 26. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 27. 5v and 3.3v ac digital block specifications symbol description min typ max units notes timer capture pulse width 50 [16] ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v maximum frequency, with capture ? ? 24.6 mhz counter enable pulse width 50 [16] ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [16] ? ? ns disable mode 50 [16] ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmis- sions 50 [16] ? ? ns transmitter maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. receiver maximum input clock frequency maximum input clock frequency with vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. note 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 29 of 34 ac analog output buffer specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 28. 5v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz table 29. 3.3v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1v step, 100 pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100 pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 30 of 34 ac external clock specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. ac programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. sar8 adc ac specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 30. 5v ac external clock specifications symbol description min typ max units f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 31. 3.3v ac external clock specifications symbol description min typ max units f oscext frequency with cpu clock divide by 1 [17] 0.093 ? 12.3 mhz f oscext frequency with cpu clock divide by 2 or greater [18] 0.186 ? 24.6 mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s notes 17. maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock di vider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 18. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this ca se, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. table 32. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 20 ? ms t write flash block write time ? 20 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 table 33. sar8 adc ac specifications symbol description min typ max units freq 3 input clock frequency 3v ? ?3.0mhz freq 5 input clock frequency 5v ? ?3.0mhz [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 31 of 34 ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 16. definition for timing for fast/standard mode on the i 2 c bus table 34. ac characteristics of the i 2 c sda and scl pins for vdd > 3.0v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ? 100 [19] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are s uppressed by the input filter. ? ?050ns table 35. ac characteristics of the i 2 c sda and scl pins for vdd < 3.0v (fast mode not supported) symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 ? ?khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c setup time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ? ? ? s t spi2c pulse width of spikes are s uppressed by the input filter. ? ? ? ?ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c note 19. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 32 of 34 packaging information this section illustrates the packaging sp ecifications for the cy8c24533 psoc device, along with the thermal impedances for each package, solder reflow peak temperature, and t he typical package capacitance on crystal pins. figure 17. 28-pin (210-mil) ssop thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 51-85079 *c table 36. thermal impedances by package package typical ja [20] 28 ssop 95c/w table 37. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf table 38. solder reflow peak temperature package minimum peak temperature [21] maximum peak temperature 28 ssop 240c 260c notes 20. t j = t a + power x ja . 21. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8c24533 document number: 001-14643 rev. *d page 33 of 34 ordering information the following table lists the cy8c24533 psoc device fa mily key package features and ordering codes. table 39. cy8c24533 psoc device family key features and ordering information package ordering code flash (kbytes) ram (bytes) temperature range digital blocks (rows of 4) analog blocks (columns of 3) digital io pins analog inputs analog outputs xres pin 28 pin (210 mil) ssop CY8C24533-24PVXI 8 256 -40c to +85c 4 4 26 12 2 no 28 pin (210 mil) ssop (tape and reel) CY8C24533-24PVXIt 8 256 -40c to +85c 4 4 26 12 2 no [+] feedback
document number: 001-14643 rev. *d revised december 05, 2008 page 34 of 34 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system , provided that the system confor ms to the i2c standard speci fication as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c24533 ? cypress semiconductor corporation, 2007-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy8c24533 psoc ? programmable system-on-chip? document number: 001-14643 rev ecn orig. of change submission date description of change ** 998721 ved see ecn new spec. *a 1149184 hmt see ecn update advance to preliminary. update features, pinout s, registers, specs., packages, package data, and order information. convert to new cypress template. *b 1411003 hmt see ecn update formatting edits. split out device. update registers and electrical specs. convert table notes to cypress template style. *c 1648723 hmt see ecn update sar adc electrical sp ecs. update inl, dnl, and vol specs. finetune specs. make data sheet final. *d 2616862 ogne/aesa 12/05/2008 changed title to: ?cy8c24533 psoc ? programmable system-on-chip?? changed names of registers on page 10. "saradc_c0" to "saradc_cr0" "saradc_c1" to "saradc_cr1" [+] feedback

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